Design and characterization of a 12-bit 10MS/s 10mW pipelined SAR ADC for CZT-based hard X-ray imager
| Publication Date: |
2018-02-24
|
|---|---|
| Publisher: |
Institute of Physics Publishing (IOP)
|
| Electronic ISSN: |
1748-0221
|
| Topics: |
Physics
|
| Published by: |
| _version_ | 1836398810490732544 |
|---|---|
| autor | F. Xue, W. Gao, Y. Duan, R. Zheng and Y. Hu |
| beschreibung | This paper presents a 12-bit pipelined successive approximation register (SAR) ADC for CZT-based hard X-ray Imager. The proposed ADC is comprised of a first-stage 6-bit SAR-based Multiplying Digital Analog Converter (MDAC) and a second-stage 8-bit SAR ADC. A novel MDAC architecture using V cm -based Switching method is employed to maximize the energy efficiency and improve the linearity of the ADC. Moreover, the unit-capacitor array instead of the binary-weighted capacitor array is adopted to improve the conversion speed and linearity of the ADC in the first-stage MDAC. In addition, a new layout design method for the binary-weighted capacitor array is proposed to reduce the capacitor mismatches and make the routing become easier and less-time-consuming. Finally, several radiation-hardened-by-design technologies are adopted in the layout design against space radiation effects. The prototype chip was fabricated in 0.18 μm mixed-signal 1.8V/3.3V process and operated at 1.8 ... |
| citation_standardnr | 6174240 |
| datenlieferant | ipn_articles |
| feed_id | 66992 |
| feed_publisher | Institute of Physics Publishing (IOP) |
| feed_publisher_url | http://www.iop.org/ |
| insertion_date | 2018-02-24 |
| journaleissn | 1748-0221 |
| publikationsjahr_anzeige | 2018 |
| publikationsjahr_facette | 2018 |
| publikationsjahr_intervall | 7984:2015-2019 |
| publikationsjahr_sort | 2018 |
| publisher | Institute of Physics Publishing (IOP) |
| quelle | Journal of Instrumentation |
| relation | http://iopscience.iop.org/1748-0221/13/02/P02027 |
| search_space | articles |
| shingle_author_1 | F. Xue, W. Gao, Y. Duan, R. Zheng and Y. Hu |
| shingle_author_2 | F. Xue, W. Gao, Y. Duan, R. Zheng and Y. Hu |
| shingle_author_3 | F. Xue, W. Gao, Y. Duan, R. Zheng and Y. Hu |
| shingle_author_4 | F. Xue, W. Gao, Y. Duan, R. Zheng and Y. Hu |
| shingle_catch_all_1 | Design and characterization of a 12-bit 10MS/s 10mW pipelined SAR ADC for CZT-based hard X-ray imager This paper presents a 12-bit pipelined successive approximation register (SAR) ADC for CZT-based hard X-ray Imager. The proposed ADC is comprised of a first-stage 6-bit SAR-based Multiplying Digital Analog Converter (MDAC) and a second-stage 8-bit SAR ADC. A novel MDAC architecture using V cm -based Switching method is employed to maximize the energy efficiency and improve the linearity of the ADC. Moreover, the unit-capacitor array instead of the binary-weighted capacitor array is adopted to improve the conversion speed and linearity of the ADC in the first-stage MDAC. In addition, a new layout design method for the binary-weighted capacitor array is proposed to reduce the capacitor mismatches and make the routing become easier and less-time-consuming. Finally, several radiation-hardened-by-design technologies are adopted in the layout design against space radiation effects. The prototype chip was fabricated in 0.18 μm mixed-signal 1.8V/3.3V process and operated at 1.8 ... F. Xue, W. Gao, Y. Duan, R. Zheng and Y. Hu Institute of Physics Publishing (IOP) 1748-0221 17480221 |
| shingle_catch_all_2 | Design and characterization of a 12-bit 10MS/s 10mW pipelined SAR ADC for CZT-based hard X-ray imager This paper presents a 12-bit pipelined successive approximation register (SAR) ADC for CZT-based hard X-ray Imager. The proposed ADC is comprised of a first-stage 6-bit SAR-based Multiplying Digital Analog Converter (MDAC) and a second-stage 8-bit SAR ADC. A novel MDAC architecture using V cm -based Switching method is employed to maximize the energy efficiency and improve the linearity of the ADC. Moreover, the unit-capacitor array instead of the binary-weighted capacitor array is adopted to improve the conversion speed and linearity of the ADC in the first-stage MDAC. In addition, a new layout design method for the binary-weighted capacitor array is proposed to reduce the capacitor mismatches and make the routing become easier and less-time-consuming. Finally, several radiation-hardened-by-design technologies are adopted in the layout design against space radiation effects. The prototype chip was fabricated in 0.18 μm mixed-signal 1.8V/3.3V process and operated at 1.8 ... F. Xue, W. Gao, Y. Duan, R. Zheng and Y. Hu Institute of Physics Publishing (IOP) 1748-0221 17480221 |
| shingle_catch_all_3 | Design and characterization of a 12-bit 10MS/s 10mW pipelined SAR ADC for CZT-based hard X-ray imager This paper presents a 12-bit pipelined successive approximation register (SAR) ADC for CZT-based hard X-ray Imager. The proposed ADC is comprised of a first-stage 6-bit SAR-based Multiplying Digital Analog Converter (MDAC) and a second-stage 8-bit SAR ADC. A novel MDAC architecture using V cm -based Switching method is employed to maximize the energy efficiency and improve the linearity of the ADC. Moreover, the unit-capacitor array instead of the binary-weighted capacitor array is adopted to improve the conversion speed and linearity of the ADC in the first-stage MDAC. In addition, a new layout design method for the binary-weighted capacitor array is proposed to reduce the capacitor mismatches and make the routing become easier and less-time-consuming. Finally, several radiation-hardened-by-design technologies are adopted in the layout design against space radiation effects. The prototype chip was fabricated in 0.18 μm mixed-signal 1.8V/3.3V process and operated at 1.8 ... F. Xue, W. Gao, Y. Duan, R. Zheng and Y. Hu Institute of Physics Publishing (IOP) 1748-0221 17480221 |
| shingle_catch_all_4 | Design and characterization of a 12-bit 10MS/s 10mW pipelined SAR ADC for CZT-based hard X-ray imager This paper presents a 12-bit pipelined successive approximation register (SAR) ADC for CZT-based hard X-ray Imager. The proposed ADC is comprised of a first-stage 6-bit SAR-based Multiplying Digital Analog Converter (MDAC) and a second-stage 8-bit SAR ADC. A novel MDAC architecture using V cm -based Switching method is employed to maximize the energy efficiency and improve the linearity of the ADC. Moreover, the unit-capacitor array instead of the binary-weighted capacitor array is adopted to improve the conversion speed and linearity of the ADC in the first-stage MDAC. In addition, a new layout design method for the binary-weighted capacitor array is proposed to reduce the capacitor mismatches and make the routing become easier and less-time-consuming. Finally, several radiation-hardened-by-design technologies are adopted in the layout design against space radiation effects. The prototype chip was fabricated in 0.18 μm mixed-signal 1.8V/3.3V process and operated at 1.8 ... F. Xue, W. Gao, Y. Duan, R. Zheng and Y. Hu Institute of Physics Publishing (IOP) 1748-0221 17480221 |
| shingle_title_1 | Design and characterization of a 12-bit 10MS/s 10mW pipelined SAR ADC for CZT-based hard X-ray imager |
| shingle_title_2 | Design and characterization of a 12-bit 10MS/s 10mW pipelined SAR ADC for CZT-based hard X-ray imager |
| shingle_title_3 | Design and characterization of a 12-bit 10MS/s 10mW pipelined SAR ADC for CZT-based hard X-ray imager |
| shingle_title_4 | Design and characterization of a 12-bit 10MS/s 10mW pipelined SAR ADC for CZT-based hard X-ray imager |
| timestamp | 2025-06-30T23:33:00.026Z |
| titel | Design and characterization of a 12-bit 10MS/s 10mW pipelined SAR ADC for CZT-based hard X-ray imager |
| titel_suche | Design and characterization of a 12-bit 10MS/s 10mW pipelined SAR ADC for CZT-based hard X-ray imager |
| topic | U |
| uid | ipn_articles_6174240 |