Search Results - (Author, Cooperation:C. Chalk)
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1Latest Papers from Table of Contents or Articles in PressT. Suzuki ; P. Arumugam ; T. Sakagami ; N. Lachmann ; C. Chalk ; A. Sallese ; S. Abe ; C. Trapnell ; B. Carey ; T. Moritz ; P. Malik ; C. Lutzko ; R. E. Wood ; B. C. Trapnell
Nature Publishing Group (NPG)
Published 2014Staff ViewPublication Date: 2014-10-03Publisher: Nature Publishing Group (NPG)Print ISSN: 0028-0836Electronic ISSN: 1476-4687Topics: BiologyChemistry and PharmacologyMedicineNatural Sciences in GeneralPhysicsKeywords: Animals ; Cell Separation ; *Cell Transplantation ; Cytokine Receptor Common beta Subunit/deficiency/*genetics ; Female ; *Genetic Therapy ; Lung/*cytology/metabolism/pathology ; Macrophages, Alveolar/*metabolism/*transplantation ; Male ; Mice ; Oligonucleotide Array Sequence Analysis ; Phenotype ; Pulmonary Alveolar Proteinosis/genetics/pathology/*therapy ; Time FactorsPublished by: -
2Articles: DFG German National LicensesStaff View
ISSN: 1573-1979Keywords: analog simulation ; analog test ; fault simulation ; fault modeling ; analog VHDLSource: Springer Online Journal Archives 1860-2000Topics: Electrical Engineering, Measurement and Control TechnologyNotes: Abstract Fault simulation is an accepted part of the test generation procedure for digital circuits. With complex analog and mixed-signal integrated circuits, such techniques must now be extended. Analog simulation is slow and fault simulation can be prohibitively expensive because of the large number of potential faults. We describe how the number of faults to be simulated in an analog circuit can be reduced by fault collapsing, and how the simulation time can be reduced by behavioral modeling of fault-free and faulty circuit blocks. These behavioral models can be implemented in SPICE or in VHDL-AMS and we discuss the merits of each approach. VHDL-AMS does potentially offer advantages in tackling this problem, but there are a number of computational difficulties to be overcome.Type of Medium: Electronic ResourceURL: